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Freescale Semiconductor Hardware Specification
MCF5271EC Rev. 1.2, 12/2004
MCF5271 Integrated Microprocessor Hardware Specification
32-bit Embedded Controller Division
The MCF5271 family is a highly integrated implementation of the ColdFire(R) family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in Table 1. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270. The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced Multiply Accumulate Unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller.
Table of Contents
1 2 3 4 5 6 7 8 9 MCF5271 Family Configurations ..................... 2 Block Diagram ................................................. 2 Features .......................................................... 4 Signal Descriptions........................................ 12 Modes of Operation....................................... 16 Design Recommendations ............................ 19 Mechanicals/Pinouts and Part Numbers ....... 27 Preliminary Electrical Characteristics............ 32 Documentation .............................................. 55
Technical Data (c) Freescale Semiconductor, Inc., 2004. All rights reserved.
MCF5271 Family Configurations
1
MCF5271 Family Configurations
Table 1. MCF5271 Family Configurations
Module ColdFire V2 Core with EMAC and Hardware Divide System Clock Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Hardware Encryption Watchdog Timer (WDT) Four Periodic Interrupt Timers (PIT) 32-bit DMA Timers QSPI UART(s) I2C General Purpose I/O Module (GPIO) JTAG - IEEE 1149.1 Test Access Port Package
2 x x x x x -- x x 4 x 3 x x x
5270
x
5271
x
100 MHz 96 8 Kbytes 64 Kbytes 2 x x x x x x x x 4 x 3 x x x
160 QFP, 160 QFP, 196 MAPBGA 196 MAPBGA
2
Block Diagram
The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5271.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 2 Freescale Semiconductor
Block Diagram
SDRAMC QSPI
EIM (To/From SRAM backdoor) CHIP SELECTS
I2C_SDA I2C_SCL UnTXD UnRXD UnRTS
EBI Arbiter INTC0 INTC1 PADI - Pin Muxing
UnCTS TnOUT TnIN FEC
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC)
UART 0
UART 1
UART 2
I2 C
QSPI
SDRAMC
D[31:0]
(To/From PADI) (To/From PADI)
4 CH DMA
DTIM 0
DTIM 1
DTIM 2
DTIM 3
A[23:0] R/W CS[3:0] TA
DREQ[2:0] DACK[2:0]
MUX
TSIZ[1:0]
BDM
JTAG_EN
V2 ColdFire CPU
DIV EMAC
TEA BS[3:0]
JTAG TAP 64 Kbytes SRAM (8Kx16)x4 8 Kbytes CACHE (1Kx32)x2 PORTS (GPIO)
CIM
Watchdog Timer
(To/From Arbiter)
SKHA
PLL CLKGEN (To/From INTC)
PIT0
PIT1
PIT2
PIT3
RNGA
MDHA Cryptography Modules
Edge Port
Figure 1. MCF5271 Block Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 3
Features
3
Features
This document contains information on a new product. Specifications and information herein are subject to change without notice.
3.1
*
Feature Overview
Version 2 ColdFire variable-length RISC processor core -- Static operation -- 32-bit address and data path on-chip -- Processor core runs at twice the bus frequency -- Sixteen general-purpose 32-bit data and address registers -- Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing -- Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms -- Illegal instruction decode that allows for 68K emulation support System debug support -- Real time trace for determining dynamic execution path -- Background debug mode (BDM) for in-circuit debugging -- Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger On-chip memories -- 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache -- 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) Fast Ethernet Controller (FEC) -- 10 BaseT capability, half duplex or full duplex -- 100 BaseT capability, half duplex or full duplex -- On-chip transmit and receive FIFOs -- Built-in dedicated DMA controller -- Memory-based flexible descriptor rings -- Media independent interface (MII) to external transceiver (PHY) Three Universal Asynchronous Receiver Transmitters (UARTs) -- 16-bit divider for clock generation -- Interrupt control logic -- Maskable interrupts -- DMA support
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
*
*
*
*
4
Freescale Semiconductor
Features
-- -- -- --
Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity Up to 2 stop bits in 1/16 increments Error-detection capabilities Modem support includes request-to-send (URTS) and clear-to-send (UCTS) lines for two UARTs
*
-- Transmit and receive FIFO buffers I2C Module -- Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads -- Fully compatible with industry-standard I2C bus -- Master or slave modes support multiple masters -- Automatic interrupt generation with programmable level Queued Serial Peripheral Interface (QSPI) -- Full-duplex, three-wire synchronous transfers -- Up to four chip selects available -- Master mode operation only -- Programmable master bit rates -- Up to 16 pre-programmed transfers Four 32-bit DMA Timers -- 20-ns resolution at 50 MHz -- Programmable sources for clock input, including an external clock option -- Programmable prescaler -- Input-capture capability with programmable trigger edge on input pin -- Output-compare with programmable mode for the output pin -- Free run and restart modes -- Maskable interrupts on input capture or reference-compare -- DMA trigger capability on input capture or reference-compare Four Periodic Interrupt Timers (PITs) -- 16-bit counter -- Selectable as free running or count down Software Watchdog Timer -- 16-bit counter -- Low power mode support Frequency Modulated Phase Locked Loop (PLL) -- Crystal or external oscillator reference -- 8 to 25 MHz reference frequency for normal PLL mode
*
*
*
*
*
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 5
Features
-- 24 to 50 MHz oscillator reference frequency for 1:1 mode -- Separate clock output pin -- Interrupt Controllers (x2) - Support for up to 41 interrupt sources organized as follows: 34 fully-programmable interrupt sources and 7 fixed-level external interrupt sources -- Unique vector number for each interrupt source -- Ability to mask any individual interrupt source or all interrupt sources (global mask-all) -- Support for hardware and software interrupt acknowledge (IACK) cycles -- Combinatorial path to provide wake-up from low power modes DMA Controller -- Four fully programmable channels -- Dual-address and single-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers -- Source/destination address pointers that can increment or remain constant -- 24-bit byte transfer counter per channel -- Auto-alignment transfers supported for efficient block movement -- Bursting and cycle steal support -- Software-programmable connections between the 12 DMA requesters in the UARTs (3), 32-bit timers (4), plus external logic (4), and the four DMA channels (4) External Bus Interface -- Glueless connections to external memory devices (e.g., SRAM, Flash, ROM, etc.) -- SDRAM controller supports 8-, 16-, and 32-bit wide memory devices -- Support for n-1-1-1 burst fetches from page mode Flash -- Glueless interface to SRAM devices with or without byte strobe inputs -- Programmable wait state generator -- 32-bit bidirectional data bus -- 24-bit address bus -- Up to eight chip selects available -- Byte/write enables (byte strobes) -- Ability to boot from external memories that are 8, 16, or 32 bits wide Chip Configuration Module (CCM) -- System configuration during reset -- Selects one of four clock modes -- Sets boot device and its data port width -- Configures output pad drive strength -- Unique part identification number and part revision number
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 6 Freescale Semiconductor
*
*
*
Features
-- Reset - Separate reset in and reset out signals - Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss of clock, PLL loss of lock - Status flag indication of source of last reset * General Purpose I/O interface -- Up to 61 bits of general purpose I/O -- Bit manipulation supported via set/clear functions -- Unused peripheral pins may be used as extra GPIO JTAG support for system level board testing
*
3.2
V2 Core Overview
The processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the MCF5271 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands as well as a complete set of instructions to process these data types. The EMAC provides superb support for execution of DSP operations within the context of a single processor at a minimal hardware cost.
3.3
Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access real-time trace and debug information. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface provided on Freescale's 683xx family of parts. The on-chip breakpoint resources include a total of 6 programmable registers--a set of address registers (with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor's supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 7
Features
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU's clock rate.
3.4
JTAG
The MCF5271 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a 330-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device's pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic. The MCF5271 implementation can do the following: * Perform boundary-scan operations to test circuit board electrical continuity * Sample MCF5271 system pins during operation and transparently shift out the result in the boundary scan register * Bypass the MCF5271 for a given circuit board test by effectively reducing the boundary-scan register to a single bit * Disable the output drive to pins during circuit-board testing * Drive output pins to stable levels
3.5
3.5.1
On-chip Memories
Cache
The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte instruction cache, an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The configuration is software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all configurations, the cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing 16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and a 8-Kbyte data array, organized as 2048 x 32 bits. If the desired address is mapped into the cache memory, the output of the data array is driven onto the ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache module includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data cache configurations, the memory operates in write-through mode and all operand writes generate an external bus cycle.
3.5.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 8 Freescale Semiconductor
Features
system stack, or for storing FEC data buffers. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. The SRAM module is also accessible by the DMA and FEC non-core bus masters. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance. As an example, system performance can be increased significantly if Ethernet packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
3.6
Fast Ethernet Controller (FEC)
The MCF5271's integrated Fast Ethernet Controller (FEC) performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions. The FEC supports connection and functionality for the 10/100 Mbps 802.3 media independent interface (MII). It requires an external transceiver (PHY) to complete the interface to the media.
3.7
UARTs
The MCF5271 contains three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an externally supplied clock. They can use DMA requests on transmit-ready and receive-ready as well as interrupt requests for servicing. Flow control is only available on two of the UARTs.
3.8
I2C Bus
The I2C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices.
3.9
QSPI
The queued serial peripheral interface module provides a high-speed synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, eliminating CPU intervention between transfers.
3.10 Cryptography
The superset device, MCF5271, incorporates small, fast, dedicated hardware accelerators for random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions allowing for the implementation of common Internet security protocol cryptography operations with performance well in excess of software-only algorithms.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 9
Features
3.11 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the MCF5271. Each timer module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference compare mode. By configuring the internal registers, each timer may be configured to assert an external signal, generate an interrupt on a particular event or cause a DMA transfer.
3.12 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter.
3.13 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.
3.14 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL), reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity, the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.
3.15 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers on the MCF5271, each of which can support up to 63 interrupt sources each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level.
3.16 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data with minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allow byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit. Other sources include the DMA timer, external sources via the DREQ signal,
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 10 Freescale Semiconductor
Features
and UARTs. The DMA controller supports single or dual address to off-chip devices or dual address to on-chip devices.
3.17 External Interface Module (EIM)
The external bus interface handles the transfer of information between the core and memory, peripherals, or other processing elements in the external address space. Features have been added to support external Flash modules, for secondary wait states on reads and writes, and a signal to support Active-Low Address Valid (a signal on most Flash memories). Programmable chip-select outputs provide signals to enable external memory and peripheral circuits, providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing. Base memory address and block size are programmable, with some restrictions. For example, the starting address must be on a boundary that is a multiple of the block size. Each chip select can be configured to provide read and write enable signals suitable for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is programmable on all chip selects, and further decoding is available for protection from user mode access or read-only access.
3.18 SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of JEDEC-compliant SDRAM devices. SD_SRAS/SD_SCAS address multiplexing is software configurable for different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the address and data buses, SD_RAS, SD_SCAS, SD_WE, SD_CS[1:0] and SD_CKE are dedicated SDRAM signals.
3.19 Reset
The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep track of what caused the last reset. The power management registers for the internal low-voltage detect (LVD) circuit are implemented in the reset module. There are six sources of reset: * External * Power-on reset (POR) * Watchdog timer * Phase locked-loop (PLL) loss of lock * PLL loss of clock * Software External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 11
Signal Descriptions
3.20 GPIO
Unused bus interface and peripheral pins on the MCF5271 can be used as discrete general-purpose inputs and outputs. These are managed by a dedicated GPIO module that logically groups all pins into ports located within a contiguous block of memory-mapped control registers. All of the pins associated with the external bus interface may be used for several different functions. Their primary function is to provide an external memory interface to access off-chip resources. When not used for this, all of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. The digital I/O pins on the MCF5271 are grouped into 8-bit ports. Some ports do not use all eight bits. Each port has registers that configure, monitor, and control the port pins.
4
Signal Descriptions
This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5271 signals, consult the MCF5235 Reference Manual (MCF5235RM).
4.1
Signal Properties
NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5270 and MCF5271 Signal Information and Muxing
Signal Name GPIO Alternate 1 Alternate 2 Dir.1 MCF5270 MCF5271 160 QFP MCF5270 MCF5271 196 MAPBGA
Table 2 lists all of the signals grouped by function. The "Dir" column is the direction for the primary function of the pin. Refer to Section 7, "Mechanicals/Pinouts and Part Numbers," for package diagrams.
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL -- -- -- -- -- -- I O 86 85 M14 N14 I O 83 82 N13 P13
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 12 Freescale Semiconductor
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name CLKOUT GPIO -- Alternate 1 Alternate 2 Dir.1 -- -- Mode Selection CLKMOD[1:0] RCON -- -- -- -- -- -- I I 20,21 79 G5,H5 K10 O MCF5270 MCF5271 160 QFP 89 MCF5270 MCF5271 196 MAPBGA K14
External Memory Interface and Ports A[23:21] A[20:0] PADDR[7:5] -- CS[6:4] -- -- -- O O 126, 125, 124 B11, C11, D11
123:115, A12, B12, C12, 112:106, 102:98 A13, B13, B14, C13, C14, D12, D13, D14, E11, E12, E13, E14, F12, F13, F14, G11, G12, G13 22:30, 33:39 G1, G2, H1, H2, H3, H4, J1, J2, J3, J4, K1, K2, K3, K4, L1, L2 M1, N1, M2, N2, P2, L3, M3, N3 P3, M4, N4, P4, L5, M5, N5, P5 B6, C6, D7, C7 N6 H11 J14 J13 P6 P7 H13 H12
D[31:16]
--
--
--
O
D[15:8] D[7:0] BS[3:0] OE TA TEA R/W TSIZ1 TSIZ0 TS TIP
PDATAH[7:0] PDATAL[7:0] PBS[7:4] PBUSCTL7 PBUSCTL6 PBUSCTL5 PBUSCTL4 PBUSCTL3 PBUSCTL2 PBUSCTL1 PBUSCTL0
-- -- CAS[3:0] -- -- DREQ1 -- DACK1 DACK0 DACK2 DREQ0
-- -- -- -- -- -- -- -- -- -- -- Chip Selects
O O O O I I O O O O O
42:49 50:52, 56:60 143:140 62 96 -- 95 -- -- 97 --
CS[7:4] CS[3:2] CS1 CS0
PCS[7:4] PCS[3:2] PCS1 --
-- SD_CS[1:0] -- --
-- -- -- --
O O O O
-- 132,131 130 129
B9, A10, C10, A11 A9, C9 B10 D10
SDRAM Controller
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 13
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name SD_WE SD_SCAS SD_SRAS SD_CKE GPIO PSDRAM5 PSDRAM4 PSDRAM3 PSDRAM2 Alternate 1 Alternate 2 Dir.1 -- -- -- -- -- -- -- -- -- -- O O O O O MCF5270 MCF5271 160 QFP 92 91 90 139 -- MCF5270 MCF5271 196 MAPBGA K13 K12 K11 E8 L12, L13
SD_CS[1:0] PSDRAM[1:0]
External Interrupts Port IRQ[7:3] IRQ2 IRQ1 PIRQ[7:3] PIRQ2 PIRQ1 -- DREQ2 -- -- -- -- FEC EMDC EMDIO ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER ETXCLK ETXEN ETXER ETXD[3:0] PFECI2C3 PFECI2C2 -- -- -- -- -- -- -- -- -- -- I2C_SCL I2C_SDA -- -- -- -- -- -- -- -- -- -- U2TXD U2RXD -- -- -- -- -- -- -- -- -- -- I2C I2C_SDA I2C_SCL PFECI2C1 PFECI2C0 -- -- -- -- DMA DACK[2:0] and DREQ[2:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: TS and DT2OUT for DACK2, TSIZ1and DT1OUT for DACK1, TSIZ0 and DT0OUT for DACK0, IRQ2 and DT2IN for DREQ2, TEA and DT1IN for DREQ1, and TIP and DT0IN for DREQ0. QSPI QSPI_CS1 PQSPI4 SD_CKE -- O -- B7 -- -- I/O I/O -- -- J12 J11 O I/O I I I I I O I I O O 151 150 9 8 7 6 5:2 159 158 157 156 155:152 D4 D5 E2 E1 D1 D2 D3, C1, C2, B1 B2 A2 C3 B3 A3, A4, C4, B4 I I I IRQ7=63 IRQ4=64 -- 65 N7, M7, L7, P8, N8 M8 L8
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 14 Freescale Semiconductor
Signal Descriptions
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT GPIO PQSPI3 PQSPI2 PQSPI1 PQSPI0 Alternate 1 Alternate 2 Dir.1 -- I2C_SCL I2C_SDA -- -- -- -- -- UARTs U2TXD U2RXD U1CTS U1RTS U1TXD U1RXD U0CTS U0RTS U0TXD U0RXD PUARTH1 PUARTH0 PUARTL7 PUARTL6 PUARTL5 PUARTL4 PUARTL3 PUARTL2 PUARTL1 PUARTL0 -- -- U2CTS U2RTS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DMA Timers DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT PTIMER7 PTIMER6 PTIMER5 PTIMER4 PTIMER3 PTIMER2 PTIMER1 PTIMER0 U2CTS U2RTS DREQ2 DACK2 DREQ1 DACK1 DREQ0 DACK0 -- -- DT2OUT -- DT1OUT -- -- -- BDM/JTAG2 DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] -- -- -- -- -- -- -- TRST TCLK TMS TDI TDO -- -- -- -- -- -- -- -- -- O O O I O I O 70 68 71 73 72 78 -- N9 P9 P10 M10 N10 K9 M12, N12, P12, L11 I O I O I O I O -- -- 66 -- 61 -- 10 11 H14 G14 M9 L9 L6 M6 E4 F4 O I I O O I I O O I -- -- 136 135 133 134 12 15 14 13 A8 A7 B8 C8 D9 D8 F3 G3 F1 F2 O O I O MCF5270 MCF5271 160 QFP 146 147 148 149 MCF5270 MCF5271 196 MAPBGA A6 C5 B5 A5
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 15
Modes of Operation
Table 2. MCF5270 and MCF5271 Signal Information and Muxing (continued)
Signal Name PST[3:0] GPIO -- Alternate 1 Alternate 2 Dir.1 -- -- Test TEST PLL_TEST -- -- -- -- -- -- Power Supplies VDDPLL VSSPLL OVDD -- -- -- -- -- -- -- -- -- I I I 87 84 M13 L14 I I 19 -- F5 O MCF5270 MCF5271 160 QFP 77:74 MCF5270 MCF5271 196 MAPBGA M11, N11, P11, L10
1, 18, 32, 41, 55, E5, E7, E10, F7, 69, 81, 94, 105, F9, G6, G8, H7, 114, 128, 138, H8, H9, J6, J8, 145 J10, K5, K6, K8 17, 31, 40, 54, A1, A14, E6, E9, 67, 80, 88, 93, F6, F8, F10, G7, 104, 113, 127, G9, H6, J5, J7, 137, 144, 160 J9, K7, P1, P14 16, 53, 103 D6, F11, G4, L4
VSS
--
--
--
I
VDD
1
--
--
--
I
NOTES: Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
5
5.1
* *
Modes of Operation
Chip Configuration Mode--Device Operating Options
Chip operating mode: -- Master mode Boot device/size: -- External device boot - 32-bit - 16-bit (Default) - 8-bit Output pad strength:
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
*
16
Freescale Semiconductor
Modes of Operation
*
*
-- Partial drive strength (Default) -- Full drive strength Clock mode: -- Normal PLL with external crystal -- Normal PLL with external clock -- 1:1 PLL Mode -- External oscillator mode (no PLL) Chip Select Configuration: -- PADDR[7:5] configured as chip select(s) and/or address line(s) - PADDR[7:5] configured as A23-A21 (default) - PADDR configured as CS6, PADDR[6:5] as A22-A21 - PADDR[7:6] configured as CS[6:5], PADDR5 as A21 - PADDR[7:5] configured as CS[6:4]
5.1.1
Chip Configuration Pins
Table 3. Configuration Pin Descriptions
Pin Chip Configuration Function Chip configuration enable Select chip operating mode Select external boot device data port size Select output pad drive strength Select clock mode Pin State/Meaning 1 Disabled 0 Enabled 1 Master 0 Reserved 00,11 External (32-bit) 10 External (8-bit) 01 External (16-bit) 1 Full 0 Partial 00 External clock mode (no VDDPLL must be supplied if a PLL PLL) mode is selected 01 1:1 PLL mode 10 Normal PLL with external clock reference 11 Normal PLL with crystal clock reference Value read defaults to 32-bit Comments Active low: if asserted, then all configuration pins must be driven appropriately for desired operation
RCON
D16 D20, D19
D21 CLKMOD1, CLKMOD0
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 17
Modes of Operation
Table 3. Configuration Pin Descriptions (continued)
Pin D25, D24 Chip Configuration Function Select chip select / address line Pin State/Meaning 00 PADDR[7:5] configured as A23-A21 (default) 10 PADDR7 configured as CS6, PADDR[6:5] as A22-A21 01 PADDR[7:6] configured as CS[6:5], PADDR5 as A21 11 PADDR[7:5] configured as CS[6:4] 0 BDM mode 1 JTAG mode Comments
JTAG_EN
Selects BDM or JTAG mode
5.2
Low Power Modes
The following features are available to support applications which require low power. * Four modes of operation: -- RUN -- WAIT -- DOZE -- STOP * Ability to shut down most peripherals independently. * Ability to shut down the external CLKOUT pin. There are four modes of operation: RUN, WAIT, DOZE, and STOP. The system enters a low power mode when the user programs the low power bits (LPMD) in the LPCR (Low Power Control Register) in the CIM before the CPU core executes a STOP instruction. This idles the CPU with no cycles active. The LPMD bits indicate to the system and clock controller to power down and stop the clocks appropriately. During STOP mode, the system clock is stopped low. A wakeup event is required to exit a low power mode and return back to RUN mode. Wakeup events consist of any of the following conditions. See the following sections for more details. 1. Any type of reset. 2. Assertion of the BKPT pin to request entry into Debug mode. 3. Debug request bit in the BDM control register to request entry into debug mode. 4. Any valid interrupt request.
5.2.1
RUN Mode
RUN mode is the normal system operating mode. Current consumption in this mode is related directly to the frequency chosen for the system clock.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 18 Freescale Semiconductor
Design Recommendations
5.2.2
WAIT Mode
WAIT mode is intended to be used to stop only the CPU core and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU core to exit from WAIT mode.
5.2.3
DOZE Mode
DOZE mode affects the CPU core in the same manner as WAIT mode, but with a different code on the CIM LPMD bits, which are monitored by the peripherals. Each peripheral defines individual operational characteristics in DOZE mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the DOZE mode and return to the RUN mode. Peripherals which are stopped will restart operation on exit from DOZE mode as defined for each peripheral.
5.2.4
STOP Mode
STOP mode affects the CPU core in the same manner as the WAIT and DOZE modes, but with a different code on the CCM LPMD bits. In this mode, all clocks to the system are stopped and the peripherals cease operation. STOP mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting STOP mode, most peripherals retain their pre-stop status and resume operation.
5.2.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). A peripheral may be disabled at anytime and will remain disabled during any low power mode of operation.
6
6.1
* * *
Design Recommendations
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5271. See application note AN1259 System Design and Layout Techniques for Noise Reduction in processor-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 19
Design Recommendations
6.2
*
Power Supply
33 F, .1 F and .01 F across each power supply
6.3
* *
Decoupling
Place the decoupling caps as close to the pins as possible, but they can be outside the footprint of the package. .1 F and .01 F at each supply input
6.4
*
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See Section 8, "Preliminary Electrical Characteristics."
6.5
*
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
6.6
* * * * * * * *
Clocking Recommendations
Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device.
6.7
6.7.1
6.7.1.1
Interface Recommendations
SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 4 shows the behavior of SDRAM signals in synchronous mode.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 20 Freescale Semiconductor
Design Recommendations
Table 4. Synchronous DRAM Signal Connections
Signal SD_SRAS Description Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SD_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAM read/write. Asserted for write operations and negated for read operations. Row address strobe. Select each memory block of SDRAMs connected to the MCF5271. One SD_CS signal selects one SDRAM block and connects to the corresponding CS signals. Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Bus clock output. Connects to the CLK input of SDRAMs.
SD_SCAS
DRAMW SD_CS[1:0] SD_CKE
BS[3:0] CLKOUT
6.7.1.2
Address Multiplexing
Table 5 shows the generic address multiplexing scheme for SDRAM configurations. All possible address connection configurations can be derived from this table.
Table 5. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address 17 16 15 14 13 12 11 10 9 17 18 19 20 17 16 15 14 13 12 11 10 9 17 18 19 20 0 1 2 3 4 5 6 7 8 16 17 18 19 32-bit port only 16-bit port only or 32-bit port with only 8 column address lines 16-bit port only when at least 9 column address lines are used Notes Related to Port Sizes 8-bit port only 8- and 16-bit ports only
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 21
Design Recommendations
Table 5. Generic Address Multiplexing Scheme (continued)
Address Pin Row Address Column Address 21 22 23 24 25 21 22 23 24 25 20 21 22 23 24 Notes Related to Port Sizes
The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF5271 to SDRAM. To use the tables, find the one that corresponds to the number of column address lines on the SDRAM and to the port size as seen by the MCF5271, which is not necessarily the SDRAM port size. For example, if two 1M x 16-bit SDRAMs together form a 2M x 32-bit memory, the port size is 32 bits. Most SDRAMs likely have fewer address lines than are shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 6. MCF5271 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 7. MCF5271MCF5271 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 8. MCF5271MCF5271 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 22 Freescale Semiconductor
Design Recommendations
Table 9. MCF5271MCF5271 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 10. MCF5271MCF5271 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF5271 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 17 0 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 19 18 21 20 23 22 25 24 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 11. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 12. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 15 2 14 3 13 4 12 5 11 6 10 7 9 8 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 13. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 21 22 23 24 25 26 27 28 29 30 31
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 23
Design Recommendations
Table 14. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 9 8 A7 18 17 A8 20 19 22 21 23 24 25 26 27 28 29 30 31
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 15. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 25 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 16. MCF5271MCF5271 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF5271 A16 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 16 1 A0 15 2 A1 14 3 A2 13 4 A3 12 5 A4 11 6 A5 10 7 A6 A9 9 8 A7 A18 A20 A22 A24 A26 A27 A28 A29 A30 A31 18 17 A8 20 19 A9 22 21 24 23 26 25 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
Table 17. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF5271 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 14 3 13 4 12 5 11 6 10 7 9 8 17 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 18. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF5271 A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 20 21 22 23 24 25 26 27 28 29 30 31
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 24 Freescale Semiconductor
Design Recommendations
Table 19. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF5271 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 9 8 A6 17 16 A7 19 18 A8 21 20 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 22 23 24 25 26 27 28 29 30 31
Table 20. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5271 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 A10 A11 A12 A13 A14 A15 A16 A17 A18 24 25 26 27 28 29 30 31
Table 21. MCF5271MCF5271 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5271 A15 A14 A13 A12 A11 A10 Pins Row Column SDRAM Pins 15 2 A0 14 3 A1 13 4 A2 12 5 A3 11 6 A4 10 7 A5 A9 9 8 A6 A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31 17 16 A7 19 18 A8 21 20 A9 23 22 25 24 26 27 28 29 30 31
A10 A11 A12 A13 A14 A15 A16 A17
6.7.1.3
SDRAM Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To interface one 2M 32-bit 4 bank SDRAM component (8 columns) to the MCF5271, the connections would be as shown in Table 22.
Table 22. SDRAM Hardware Connections
SDRAM Pins MCF5271 Pins A0 A15 A1 A14 A2 A13 A3 A12 A4 A11 A5 A10 A6 A9 A7 A17 A8 A18 A9 A19 A10 = CMD A20 BA0 A21 BA1 A22
6.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 23.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 25
Design Recommendations
Table 23. MII Mode
Signal Description Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data MCF5271 Pin ETXCLK ETXEN ETXD[3:0] ETXER ECOL ECRS ERXCLK ERXDV ERXD[3:0] ERXER EMDC EMDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5271 configuration for seven-wire serial mode connections to the external transceiver are shown in Table 24.
Table 24. Seven-Wire Mode Configuration
Signal Description Transmit clock Transmit enable Transmit data Collision Receive clock Receive enable Receive data Unused, configure as PB14 Unused input, tie to ground Unused, configure as PB[13:11] Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground MCF5271 Pin ETXCLK ETXEN ETXD[0] ECOL ERXCLK ERXDV ERXD[0] ERXER ECRS ERXD[3:1] ETXER ETXD[3:1] EMDC EMDIO
Refer to the M5271EVB evaluation board user's manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5271 site by navigating to: http://www.freescale.com.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 26 Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
6.7.3
BDM
Use the BDM interface as shown in the M5271EVB evaluation board user's manual. The schematics for this board are accessible at the MCF5271 site by navigating from: http://www.freescale.com following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5271 and M5271EVB links.
7
Mechanicals/Pinouts and Part Numbers
This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF5271 devices. See Table 2 for a list the signal names and pin locations for each device.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 27
Mechanicals/Pinouts and Part Numbers
7.1
1 A VSS
Pinout--196 MAPBGA
2 ETXCLK 3 ETXD3 4 ETXD2 5 QSPI_ DOUT QSPI_DIN 6 QSPI_CS0 7 U2RXD 8 U2TXD 9 CS3 10 CS6 11 CS4 12 A20 13 A17 14 VSS A
Figure 2 shows a pinout of the MCF5270/71CVMxxx package.
B
ERXD0
ERXER
ETXER
ETXD0
BS3
QSPI_CS1
U1CTS
CS7
CS1
A23
A19
A16
A15
B
C
ERXD2
ERXD1
ETXEN
ETXD1
QSCK
BS2 Core VDD_4 VSS
BS0
RTS1
CS2
CS5
A22
A18
A14
A13
C
D
ERXCLK
ERXDV
ERXD3
EMDC
EMDIO
BS1
U1RXD1
U1TXD
CS0
A21
A12
A11
A10
D
E
ECRS
ECOL
NC
TIN0
VDD
VDD
SD_CKE
VSS
VDD
A9 Core VDD_3 A2
A8
A7
A6
E
F
U0TXD
U0RXD
U0CTS
DTOUT0 Core VDD_1 DATA26
TEST CLK MOD1 CLK MOD0 VSS
VSS
VDD
VSS
VDD
VSS
A5
A4
A3
F
G
Data31
DATA30
U0RTS
VDD
VSS
VDD
VSS
NC
A1
A0
DTOUT3
G
H
DATA29
DATA28
DATA27
VSS
VDD
VDD
VDD
NC
TA
TIP
TS
DTIN3
H
J
DATA25
DATA24
DATA23
DATA22
VDD
VSS
VDD
VSS
VDD
I2C_SCL
I2C_SDA
R/W
TEA
J
K
DATA21
DATA20
DATA19
DATA18 Core VDD_2 DATA6
VDD
VDD
VSS
VDD
JTAG_EN
RCON
SD_ RAS
SD_ CAS
SD_ WE
CLKOUT
K
L
DATA17
DATA16
DATA10
DATA3
DTIN1
IRQ5
IRQ1
DTOUT2
PST0
DDATA0
SD_ CS1
SD_ CS0
VSSPLL
L
M
DATA15
DATA13
DATA9
DATA2
DTOUT1
IRQ6
IRQ2
DTIN2 TRST/ DSCLK TCLK/ PSTCLK 9
TDI/DSI
PST3
DDATA3
VDDPLL
EXTAL
M
N
DATA14
DATA12
DATA8
DATA5
DATA1
OE
IRQ7
IRQ3
TDO/DSO TMS/ BKPT 10
PST2
DDATA2
RESET
XTAL
N
P
VSS 1
DATA11 2
DATA7 3
DATA4 4
DATA0 5
TSIZ1 6
TSIZ0 7
IRQ4 8
PST1 11
DDATA1 12
RSTOUT 13
VSS 14
P
Figure 2. MCF5270/71CVMxxx Pinout (196 MAPBGA)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 28 Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
7.2
Package Dimensions--196 MAPBGA
Figure 3 shows MCF5270/71CVMxxx package dimensions.
X Y
D Laser mark for pin 1 identification in this area K
M
NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension B is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
Millimeters DIM Min Max
E
A A1 A2 b D E e S M 0.20
13X
1.32 1.75 0.27 0.47 1.18 REF 0.35 0.65 15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
e Metalized mark for pin 1 identification in this area
A B C
S
14 13 12 11 10 9 6 5 4 3 2 1
S
13X
D E F G H J K L M N
5 A A2 0.30 Z
e
A1
Z
4
0.15 Z
Detail K Rotated 90 Clockwise
3
196X
P
b 0.30 Z X Y 0.10 Z View M-m
Figure 3. 196 MAPBGA Package Dimensions (Case No. 1128A-01)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 29
Mechanicals/Pinouts and Part Numbers
7.3
Pinout--160 QFP
VSS ERXER ETXCLK ETXEN ETXER ETXD3 ETXD2 ETXD1 ETXD0 EMDC EMDIO QSPI_DOUT QSPI_DIN QSPI_CLK QSPI_CS0 O-VDD VSS BS3 BS2 BS1 BS0 SD_CKE/QSPI_CS1 O-VDD VSS U1CTS U1RTS U1RXD U1TXD CS3 CS2 CS1 CS0 O-VDD VSS A23 A18 A21 A20 A19 A18 O-VDD ERXD0 ERXD1 ERXD2 ERXD3 ERXDV ERXCLK ECRS ECOL U0TIN U0TOUT U0CTS U0RXD U0TXD U0RTS Core VDD_1 VSS O-VDD TEST CLKMOD1 CLKMOD0 DATA31 DATA30 DATA29 DATA28 DATA27 DATA26 DATA25 DATA24 DATA23 VSS O-VDD DATA22 DATA21 DATA20 DATA19 DATA18 DATA17 DATA16 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Figure 4 shows a pinout of the MCF5271CABxxx package.
MCF5271
A17 A16 A15 A14 A13 A12 O-VDD VSS A11 A10 A9 A8 A7 A6 A5 O-VDD VSS Core_Vdd_3 A4 A3 A2 A1 A0 TS TA R/W O-VDD VSS SD_WE SD_SCAS SD_SRAS CLKOUT VSS VDDPLL EXTAL XTAL VSSPLL RESET RSTOUT O-VDD
30
O-VDD DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 Core Vdd_2 VSS O-VDD DATA4 DATA3 DATA2 DATA1 DATA0 DTIN1 OE IRQ7 IRQ4 IRQ1 DTIN2 VSS TCLK\PSTCLK O-VDD TRST/DSCLK TMS\BKPT TDO/DSO TDI/DSI PST0 PST1 PST2 PST3 JTAG_EN RCON VSS
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Figure 4. MCF5270/71CABxxx Pinout (160 QFP)
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor
Mechanicals/Pinouts and Part Numbers
7.4
Package Dimensions--160 QFP
Y L
Figure 5 shows MCF5270/71CAB80 package dimensions.
DS
DS
-A-, -B-, -D-
A-B S
M
A-B
-A- L
H
B
V
0.20 (0.008)
0.20 (0.008)
0.20 (0.008) M
H
-B-
A-B
S
B
B
P G DETAIL A
DETAIL A
Z A
0.20 (0.008) M C 0.20 (0.008) A-B A-B
S
DS
BASE METAL
S
0.20 (0.008) MC A-B
S
N
DS
J F D
DETAIL C
0.13 (0.005) M
-H-
C A-B
S
DS
SECTION B-B
MILLIMETERS DIM MIN MAX A 27.90 28.10 27.90 28.10 B 3.85 3.35 C 0.22 0.38 D 3.20 3.50 E 0.22 0.33 F 0.65 BSC G H 0.25 0.35 0.11 0.23 J K 0.70 0.90 25.35 BSC L 5 16 M 0.11 0.19 N 0.325 BSC P Q 7 0 R 0.13 0.30 S 31.00 31.40 0.13 -- T U 0 -- V 31.00 31.40 0.4 -- W 1.60 REF X Y 1.33 REF 1.33 REF Z INCHES MIN MAX 1.098 1.106 1.098 1.106 0.132 1.106 0.009 0.015 0.126 0.138 0.009 0.013 0.026 REF 0.010 0.014 0.004 0.009 0.028 0.035 0.998 REF 5 16 0.004 0.007 0.013 REF 0 7 0.005 0.012 1.220 1.236 0.005 -- 0 -- 1.220 1.236 0.016 -- 0.063 REF 0.052 REF 0.052 REF
Mx
TOP & BOTTOM
NOTES 1. DIMENSIONING AND TOLERINCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLAN -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B-, AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
Ux C E -H-
T R Qx
-C- H
W K X
0.110 (0.004)
DETAIL C
Case 864A-03
Figure 5. 160 QFP Package Dimensions
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 31
Preliminary Electrical Characteristics
7.5
Ordering Information
Table 25. Orderable Part Numbers
Freescale Part Number PCF5270AB100 PCF5270VM100 PCF5271CAB100 Description MCF5270 RISC Microprocessor, 160 QFP MCF5270 RISC Microprocessor, 196 MAPBGA MCF5271 RISC Microprocessor, 160 QFP MCF5271 RISC Microprocessor, 196 MAPBGA Speed 100MHz 100MHz 100MHz 100MHz Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C
PCF5271CVM100
8
Preliminary Electrical Characteristics
This chapter contains electrical specification tables and reference timing diagrams for the MCF5271 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5271. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this processor document supersede any values found in the module specifications.
8.1
Maximum Ratings
Table 26. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage Pad Supply Voltage Clock Synthesizer Supply Voltage Digital Input Voltage
3
Symbol VDD OVDD VDDPLL VIN ID TA (TL - TH) Tstg
Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to + 4.0 25 - 40 to 85 - 65 to 150
Unit V V V V mA C C
Instantaneous Maximum Current Single pin limit (applies to all pins) 3,4,5 Operating Temperature Range (Packaged) Storage Temperature Range
NOTES: 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Continued operation at these levels may affect device reliability or cause permanent damage to the device.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 32 Freescale Semiconductor
Preliminary Electrical Characteristics
2
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or OVDD). 3 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 4 All functional non-supply pins are internally clamped to VSS and OVDD. 5 Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > OVDD) is greater than IDD, the injection current may flow out of OVDD and could result in external power supply going out of regulation. Insure external OVDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power (ex; no clock).Power supply must maintain regulation within operating OVDD range during instantaneous and operating maximum current conditions.
8.2
Thermal Characteristics
Table 27. Thermal Characteristics
Characteristic Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature Four layer board (2s2p) Four layer board (2s2p) Symbol JMA JMA JB JC jt Tj 196 160QFP MAPBGA 321,2 295,6 205 107 25,9 104 403,4 365,6 25
6
Table 27 lists thermal resistance values
Unit C/W C/W C/W C/W C/W
oC
108 25,10 105
NOTES: 1 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Motorola recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 4 Per JEDEC JESD51-6 with the board horizontal. 5 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 6 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 33
Preliminary Electrical Characteristics
7
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 8 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 9 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. 10 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in C can be obtained from:
T J = T A + ( P D x JMA ) (1)
Where: TA= Ambient Temperature, C JMA= Package Thermal Resistance, Junction-to-Ambient, C/W PD= PINT + PI/O PINT= IDD x VDD, Watts - Chip Internal Power PI/O= Power Dissipation on Input and Output Pins -- User Determined For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is:
P D = K / ( T J + 273C ) (2)
Solving equations 1 and 2 for K gives:
K = PD x (TA + 273 C) + JMA x PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.
8.3
DC Electrical Specifications
Table 28. DC Electrical Specifications1
Characteristic Symbol VDD OVDD VIH VIL VHYS Iin Min 1.35 3 0.7 OVDD VSS - 0.3 0.06 OVDD -1.0 Typical -- -- -- -- -- -- Max 1.65 3.6 3.65 0.35 OVDD -- 1.0 Unit V V V V mV A
Core Supply Voltage Pad Supply Voltage Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Vin = VDD or VSS, Input-only pins
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 34 Freescale Semiconductor
Preliminary Electrical Characteristics
Table 28. DC Electrical Specifications1 (continued)
Characteristic High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins Output High Voltage (All input/output and all output pins) IOH = -5.0 mA Output Low Voltage (All input/output and all output pins) IOL = 5.0mA Weak Internal Pull Up Device Current, tested at VIL Max.2 Input Capacitance All input-only pins All input/output (three-state) pins Load Capacitance4 Low drive strength High drive strength Core Operating Supply Current 5 Master Mode Pad Operating Supply Current Master Mode Low Power Modes DC Injection Current 3, 6, 7, 8 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total processor Limit, Includes sum of all stressed pins
3
Symbol IOZ VOH VOL IAPU Cin
Min -1.0 OVDD - 0.5 __ -10 -- --
Typical -- -- -- -- --
Max 1.0 __ 0.5 - 130 7 7
Unit A V V A pF
-- CL IDD -- OIDD -- -- IIC -1.0 -10 1.0 10 100 TBD -- -- 135 150 25 50
pF
mA mA A mA
NOTES: 1 Refer to Table 29 for additional PLL specifications. 2 Refer to the MCF5271 signals section for pins having weak internal pull-up devices. 3 This parameter is characterized before qualification rather than 100% tested. 4 pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. See High Speed Signal Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines. 5 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 6 All functional non-supply pins are internally clamped to VSS and their respective VDD. 7 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the processor is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 35
Preliminary Electrical Characteristics
8.4
Oscillator and PLLMRFM Electrical Characteristics
Table 29. HiP7 PLLMRFM Electrical Specifications1
Num 1 Characteristic PLL Reference Frequency Range Crystal reference External reference 1:1 mode (NOTE: fsys/2 = 2 x fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Loss of Reference Frequency 3, 5 Self Clocked Mode Frequency 4, 5 Crystal Start-up Time 5, 6 XTAL Load Capacitance5 PLL Lock Time 5, 7,13 Power-up To Lock Time 5, 6,8 With Crystal Reference (includes 5 time) Without Crystal Reference9 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 10 Duty Cycle of reference 5 Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, 5, 6, 8,11, 12 Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit13,14 (fsys/2 Max must not be exceeded) ICO Frequency. fico = fref * 2 * (MFD+2) 15 tlpll tlplk -- -- tskew tdc fUL fLCK Cjitter -- -- 5.0 .01 % fsys/2 -1 40 -3.8 -1.7 11 750 1 60 4.1 2.0 ms s ns % % fsys/2 % fsys/2 Symbol Min. Value Max. Value Unit MHz fref_crystal fref_ext fref_1:1 fsys fsys/2 fLOR fSCM tcst 0 fref / 32 100 10.25 -- 5 -- 8 8 24 25 25 50 100 50 50 1000 15.25 10 30 750 MHz MHZ MHz kHz MHz ms pF s
2
3 4 5 6 7 8
9 10 11 12 13
14 15
Cmod fico
0.8 48
2.2 75
%fsys/2 MHz
NOTES: 1 All values given are initial design targets and subject to change. 2 All internal registers retain data at 0 Hz. 3 "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. 4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. 5 This parameter is guaranteed by characterization before qualification rather than 100% tested. 6 Proper PC board layout procedures must be followed to achieve specifications.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 36 Freescale Semiconductor
Preliminary Electrical Characteristics
7 8
9 10 11
12 13 14 15
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDSYN are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. tlpll = (64 * 4 * 5 + 5 ) Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and = 1.57x10-6 2(MFD + 2). PLL is operating in 1:1 PLL mode. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the Cjitter percentage for a given interval. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of Cjitter+Cmod. Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz. Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. fsys/2 = fico / (2 * 2RFD)
8.5
External Interface Timing Characteristics
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values.
Table 30. Processor Bus Input Timing Specifications
Table 30 lists processor bus input timings.
Name freq B0 System bus frequency CLKOUT period
Characteristic1
Symbol fsys/2 tcyc
Min 50
Max 50 1/50
Unit MHz ns
Control Inputs B1a B1b B2a B2b Control input valid to CLKOUT high BKPT valid to CLKOUT high
3 2
tCVCH tBKVCH tCHCII tBKNCH
9 9 0 0
-- -- -- --
ns ns ns ns
CLKOUT high to control inputs invalid2 CLKOUT high to asynchronous control input BKPT invalid3 Data Inputs
B4 B5
Data input (D[31:0]) valid to CLKOUT high CLKOUT high to data input (D[31:0]) invalid
tDIVCH tCHDII
4 0
-- --
ns ns
NOTES: 1 Timing specifications are tested using full drive strength pad configurations in a 50ohm transmission line environment.. 2 TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 37
Preliminary Electrical Characteristics
Timings listed in Table 30 are shown in Figure 6 & Figure A-3.
* The timings are also valid for inputs sampled on the negative clock edge. CLKOUT(75MHz) TSETUP THOLD 1.5V
Input Setup And Hold
Invalid
1.5V Valid 1.5V
Invalid
trise Input Rise Time Vh = VIH Vl = VIL
tfall Input Fall Time Vh = VIH Vl = VIL
CLKOUT
B4 B5
Inputs
Figure 6. General Input Timing Requirements
8.6
Processor Bus Output Timing Specifications
Table 31. External Bus Output Timing Specifications
Name Characteristic Control Outputs Symbol Min Max Unit
Table 31 lists processor bus output timings.
B6a B6b B6c B7 B7a
CLKOUT high to chip selects valid 1 CLKOUT high to byte enables (BS[3:0]) valid2 CLKOUT high to output enable (OE) valid3 CLKOUT high to control output (BS[3:0], OE) invalid CLKOUT high to chip selects invalid
tCHCV tCHBV tCHOV tCHCOI tCHCI
-- -- -- 0.5tCYC+1.5 0.5tCYC+1.5
0.5tCYC +5 0.5tCYC +5 0.5tCYC +5 -- --
ns ns ns ns ns
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 38 Freescale Semiconductor
Preliminary Electrical Characteristics
Table 31. External Bus Output Timing Specifications (continued)
Name Characteristic Symbol Min Max Unit
Address and Attribute Outputs B8 B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid Data Outputs B11 B12 B13
1
tCHAV tCHAI
-- 1.5
9 --
ns ns
CLKOUT high to data output (D[31:0]) valid CLKOUT high to data output (D[31:0]) invalid CLKOUT high to data output (D[31:0]) high impedance
tCHDOV tCHDOI tCHDOZ
-- 1.5 --
9 -- 9
ns ns ns
NOTES: CS transitions after the falling edge of CLKOUT. 2 BS transitions after the falling edge of CLKOUT. 3 OE transitions after the falling edge of CLKOUT.
Read/write bus timings listed in Table 31 are shown in Figure 7, Figure 8, and Figure 9.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 39
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT B7a CSn A[23:0] TSIZ[1:0] TS TIP B8 B6c OE B7 B9 R/W (H) B6b BS[3:0] B4 D[31:0] B5 TA (H) B13 B7 B11 B12 B8 B6b B7 B0 B7a B6a B8 B9
B6a
B8
B8 B9 B8
B9 B9
TEA (H)
Figure 7. Read/Write (Internally Terminated) SRAM Bus Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 40 Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 8 shows a bus cycle terminated by TA showing timings listed in Table 31.
S0 CLKOUT CSn B6a
B7a
S1
S2
S3
S4
S5
S0
S1
B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP OE B6c B7 R/W (H) B9
B9
B9
BS[3:0]
B6b
B7 B5 B4
D[31:0] TA B1a B2a
TEA (H)
Figure 8. SRAM Read Bus Cycle Terminated by TA
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 41
Preliminary Electrical Characteristics
Figure 9 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 31.
S0
CLKOUT CSn B6a B7a S1 S2 S3 S4 S5 S0 S1
B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP OE B6c B7 B9
B9
B9
R/W (H)
BS[3:0]
B6b
B7
D[31:0]
TA (H)
B1a TEA
B2a
Figure 9. SRAM Read Bus Cycle Terminated by TEA
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 42 Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 10 shows an SDRAM read cycle.
0 SD_CKE
D1 D3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A[23:0]
D2
Row
Column
D4
RAS
D2
D4
CAS 1
D4 D2
SDWE
D5
D6
D[31:0]
D2
RAS[1:0]
D2 D4
CAS[3:0]
ACTV 1 DACR[CASL] NOP READ NOP NOP PALL
=2
Figure 10. SDRAM Read Cycle Table 32. SDRAM Timing
NUM D1 D2 D3 D4 D5 D6 D71 D82 Characteristic CLKOUT high to SDRAM address valid CLKOUT high to SDRAM control valid CLKOUT high to SDRAM address invalid CLKOUT high to SDRAM control invalid SDRAM data valid to CLKOUT high CLKOUT high to SDRAM data invalid CLKOUT high to SDRAM data valid CLKOUT high to SDRAM data invalid Symbol tCHDAV tCHDCV tCHDAI tCHDCI tDDVCH tCHDDI tCHDDVW tCHDDIW Min -- -- 1.5 1.5 4 1.5 -- 1.5 Max 9 9 -- -- -- -- 9 -- Unit ns ns ns ns ns ns ns ns
NOTES: 1 D7 and D8 are for write cycles only.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 43
Preliminary Electrical Characteristics
Figure 11 shows an SDRAM write cycle.
0 SD_CKE
D1 D3
1
2
3
4
5
6
7
8
9
10
11
12
A[23:0]
D2
Row
Column
D4
SD_SRAS
D2
SD_SCAS1
D2 D4
SD_WE
D7
D[31:0]
D2 D8
RAS[1:0]
D2 D4
CAS[3:0]
ACTV 1 DACR[CASL] NOP WRITE NOP PALL
=2
Figure 11. SDRAM Write Cycle
8.7
NUM G1 G2 G3 G4
General Purpose I/O Timing
Table 33. GPIO Timing1
Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.5 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
NOTES: 1 GPIO pins include: INT, UART, and Timer pins.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 44 Freescale Semiconductor
Preliminary Electrical Characteristics
CLKOUT
G1
GPIO Outputs
G2
G3
GPIO Inputs
G4
Figure 12. GPIO Timing
8.8
Reset and Configuration Override Timing
Table 34. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM R1 R2 R3 R4 R5 R6 R7 R8
Characteristic RESET Input valid to CLKOUT High CLKOUT High to RESET Input invalid RESET Input valid Time
2
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1
Unit ns ns tCYC ns ns tCYC ns tCYC
CLKOUT High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
NOTES: 1 All AC timing is shown with respect to 50% VDD levels unless otherwise noted. 2 During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 45
Preliminary Electrical Characteristics
CLKOUT
R1 R3
RESET
R2
R4
RSTOUT
R4 R8 R5 R6 R7
Configuration Overrides*: (RCON, Override pins])
Figure 13. RESET and Configuration Override Timing
* Refer to the Coldfire Integration Module (CIM) section for more information.
8.9
I2C Input/Output Timing Specifications
Table 35. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 I6 I7 I8 I9 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 -- 0 -- 4 0 2 2 Max -- -- 1 -- 1 -- -- -- -- Units tcyc tcyc ms ns ms tcyc ns tcyc tcyc
Table 35 lists specifications for the I2C input timing parameters shown in Figure 14.
Table 36 lists specifications for the I2C output timing parameters shown in Figure 14.
Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I11 I2 1 I3 2 I4 1 I5
3
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time
Min 6 10 -- 7 -- 10
Max -- -- -- -- 3 --
Units tcyc tcyc s tcyc ns tcyc
I6 1
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 46 Freescale Semiconductor
Preliminary Electrical Characteristics
Table 36. I2C Output Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num I7 1 I8
1
Characteristic Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 2 20 10
Max -- -- --
Units tcyc tcyc tcyc
I9 1
NOTES: 1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 36. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 36 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 14 shows timing for the values in Table 35 and Table 36.
I2 I6 I5
I2C_SCL I1 I4 I7 I8
I3
I9
I2C_SDA
Figure 14. I2C Input/Output Timings
8.10 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
8.10.1 MII Receive Signal Timing (ERXD[3:0], ERXDV, ERXER, and ERXCLK)
The receiver functions correctly up to a ERXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the ERXCLK frequency. Table 37 lists MII receive channel timings.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 47
Preliminary Electrical Characteristics
Table 37. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic ERXD[3:0], ERXDV, ERXER to ERXCLK setup ERXCLK to ERXD[3:0], ERXDV, ERXER hold ERXCLK pulse width high ERXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns ERXCLK period ERXCLK period
Figure 15 shows MII receive signal timings listed in Table 37.
M3
ERXCLK (input)
ERXD[3:0] (inputs) ERXDV ERXER M1 M2
M4
Figure 15. MII Receive Signal Timing Diagram
8.10.2 MII Transmit Signal Timing (ETXD[3:0], ETXEN, ETXER, ETXCLK)
Table 38 lists MII transmit channel timings. The transmitter functions correctly up to a ETXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the ETXCLK frequency. The transmit outputs (ETXD[3:0], ETXEN, ETXER) can be programmed to transition from either the rising or falling edge of ETXCLK, and the timing is the same in either case. This options allows the use of non-compliant MII PHYs. Refer to the Ethernet chapter for details of this option and how to enable it.
Table 38. MII Transmit Signal Timing
Num M5 M6 M7 M8 Characteristic ETXCLK to ETXD[3:0], ETXEN, ETXER invalid ETXCLK to ETXD[3:0], ETXEN, ETXER valid ETXCLK pulse width high ETXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns ETXCLK period ETXCLK period
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 48 Freescale Semiconductor
Preliminary Electrical Characteristics
Figure 16 shows MII transmit signal timings listed in Table 38.
M7
ETXCLK (input) M5 ETXD[3:0] (outputs) M8
ETXEN
ETXER M6
Figure 16. MII Transmit Signal Timing Diagram
8.10.3 MII Async Inputs Signal Timing (ECRS and ECOL)
Table 39 lists MII asynchronous inputs signal timing.
Table 39. MII Async Inputs Signal Timing
Num M9 Characteristic ECRS, ECOL minimum pulse width Min 1.5 Max -- Unit ETXCLK period
Figure 17 shows MII asynchronous input timings listed in Table 39.
ECRS, ECOL M9
Figure 17. MII Async Inputs Timing Diagram
8.10.4 MII Serial Management Channel Timing (EMDIO and EMDC)
Table 40 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 40. MII Serial Management Channel Timing
Num M10 M11 M12 M13 M14 M15 Characteristic EMDC falling edge to EMDIO output invalid (minimum propagation delay) EMDC falling edge to EMDIO output valid (max prop delay) EMDIO (input) to EMDC rising edge setup EMDIO (input) to EMDC rising edge hold EMDC pulse width high EMDC pulse width low Min 0 -- 10 0 Max -- 25 -- -- Unit ns ns ns ns
40% 60% MDC period 40% 60% MDC period
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 49
Preliminary Electrical Characteristics
Figure 18 shows MII serial management channel timings listed in Table 40.
M14 M15
EMDC (output)
M10
EMDIO (output)
M11
EMDIO (input)
M12
M13
Figure 18. MII Serial Management Channel Timing Diagram
8.11 32-Bit Timer Module AC Timing Specifications
Table 41 lists timer module AC timings.
Table 41. Timer Module AC Timing Specifications
0-66 MHz Name T1 T2 Characteristic Min DT0IN / DT1IN / DT2IN / DT3IN cycle time DT0IN / DT1IN / DT2IN / DT3IN pulse width 3 1 Max -- -- tCYC tCYC Unit
8.12 QSPI Electrical Specifications
Table 42 lists QSPI timings.
Table 42. QSPI Modules AC Timing Specifications
Name QS1 QS2 QS3 QS4 QS5 QSPI_CS[1:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid. (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Characteristic Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tcyc ns ns ns ns
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 50 Freescale Semiconductor
Preliminary Electrical Characteristics
The values in Table 42 correspond to Figure 19.
QS1 QSPI_CS[1:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 19. QSPI Timing
8.13 JTAG and Boundary Scan Timing
Table 43. JTAG and Boundary Scan Timing
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 3 33 33 26 8 Unit fsys/2 tCYC ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 51
Preliminary Electrical Characteristics
J2 J3 J3
TCLK (input)
J4
VIH VIL J4
Figure 20. Test Clock Input Timing
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 21. Boundary Scan (JTAG) Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 52 Freescale Semiconductor
Preliminary Electrical Characteristics
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 22. Test Access Port Timing
TCLK
J14
TRST
J13
Figure 23. TRST Timing
8.14 Debug AC Timing Specifications
Table 44 lists specifications for the debug AC timing parameters shown in Figure 25.
Table 44. Debug AC Timing Specification
150 MHz Num DE0 DE1 DE2 DE3 DE4 Characteristic Min PSTCLK cycle time PST valid to PSTCLK high PSTCLK high to PST invalid DSCLK cycle time DSI valid to DSCLK high 4 1.5 5 1 Max 0.5 tcyc ns ns tcyc tcyc Units
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 53
Preliminary Electrical Characteristics
Table 44. Debug AC Timing Specification (continued)
150 MHz Num DE5 1 DE6 DE7
1
Characteristic Min DSCLK high to DSO invalid BKPT input data setup time to CLKOUT Rise CLKOUT high to BKPT high Z 4 4 0 10 Max
Units tcyc ns ns
NOTES: DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of CLKOUT.
Figure 24 shows real-time trace timing for the values in Table 44.
PSTCLK
DE0 DE1 DE2
PST[3:0] DDATA[3:0]
Figure 24. Real-Time Trace AC Timing
Figure 25 shows BDM serial port AC timing for the values in Table 44.
CLKOUT DE6 BKPT DE7 DE5
DSCLK DE3 DSI Current DE4 DSO Past Current Next
Figure 25. BDM Serial Port AC Timing
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 54 Freescale Semiconductor
Documentation
9
Documentation
Table 45 lists the documents that provide a complete description of the MCF5271 and their development support tools. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale world-wide web address at http://www.freescale.com.
Table 45. MCF5271 Documentation
Freescale Document Number
MCF5271EC MCF5271RM MCF5271PB MCF5271FS CFPRODFACT/D MCF5xxxWP MAPBGAPP CFPRM/D
Title
MCF5271 RISC Microprocessor Hardware Specifications MCF5271 Reference Manual MCF5271 Product Brief MCF5271 Fact Sheet The ColdFire Family of 32-Bit Microprocessors Family Overview and Technology Roadmap MCF5xxxWP WHITE PAPER: Motorola ColdFire VL RISC Processors MAPBGA 4-Layer Example ColdFire Family Programmer's Reference Manual
Revision
Rev. 1.2 1.1 0 -- 0 0 0 2
Status
This document Available Available In Process Available under NDA Available under NDA Available Available
9.1
Document Revision History
Table 46. Document Revision History
Rev. No. 0 1 1.1 1.2 Initial release - Fixed several clock values. - Updated Signal List table - Removed duplicate information in the module description sections. The information is all in the Signals Description Table. - Removed detailed signal description section. This information can be found in the MCF5235RM Chapter 2. - Removed detailed feature list. This information can be found in the MCF5235RM Chapter 1. - Changed instances of Motorola to Freescale - Added values for `Maximum operating junction temperature' in Table 27. - Added typical values for `Core operating supply current (master mode)' in Table 28. - Added typical values for `Pad operating supply current (master mode)' in Table 28. - Removed unnecessary PLL specifications, #6-9, in Table 29. Substantive Change(s)
Table 46 provides a revision history for this document.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 55
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2004.
MCF5271EC Rev. 1.2, 12/2004

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